The memory cells of the portless, five-transistor SRAM type are well known to those skilled in the art. Notably worth citing is the article by Michael Wieckowski and Martin Margala entitled “Portless SRAM—A High-Performance Alternative to the 6T Methodology,” IEEE Journal of Solid-State Circuits, Volume 42, No. 11, November 2007, or the article by these same authors entitled “A Portless SRAM Cell Using Stunted Wordline Drivers,” IEEE 2008, pages 584-587.
A memory cell of the portless SRAM type is, as diagrammatically illustrated in FIG. 1, based on the principle of two inverters INV1, INV2, cross-coupled and powered by two portless bit lines BLTP and BLFP, such as, for example, NMOS transistors.
Furthermore, the SRAM cell comprises a fifth transistor, called “access transistor,” AXS, connected as illustrated in FIG. 1.
FIG. 2 illustrates a more detailed, but still diagrammatic, representation of the cell of FIG. 1, in which the transistors of the inverters are represented. More specifically, the cell CEL effectively comprises five transistors, namely two pairs of PMOS and NMOS transistors forming the two inverters, and the fifth transistor AXS. FIG. 2 shows that the source of the PMOS transistor M1 is connected to the bit line BLTP, whereas the source of the PMOS transistor M3 is connected to the line BLFP. The drains of these two transistors M1 and M3 are respectively connected to the drains of the two NMOS transistors M2 and M4. The sources of these two transistors M2 and M4 are connected to the ground.
Moreover, the gates of the four transistors M1-M4 are cross-coupled. Finally, the access transistor AXS, which is in this case an NMOS transistor, is connected between the gates of the PMOS transistors M1 and M3. That said, this transistor AXS could be a PMOS transistor.
A datum, comprising two complementary logic values 1, 0 or 0, 1, is stored between the two output nodes T and F of the two inverters. For example, the two nodes T and F of the two inverters may store 1 and 0, respectively, or 0 and 1, respectively.
When the access transistor AXS is opened (blocked or OFF), the cell CEL is stable and the datum is kept in that cell as long as the cell remains powered by the power supply voltage. When the access transistor AXS is closed (passing or ON), a current flows from the node T or F presenting the logic value 1 to the node F or T presenting the logic value 0.
A portless, five-transistor SRAM cell is therefore an alternative to the conventional six-transistor SRAM cells, that is to say with two inverters connected to the two bit lines by two ports, such as NMOS transistors.
To write a datum into the cell CEL, the two bit lines are first of all precharged at the power supply voltage, the transistor AXS is closed and the voltage of one of the bit lines is made to drop depending on whether the desire is to write a 1 or a 0, so as to provoke a voltage difference between the nodes T and F of the cell.
Once the datum is written, the transistor AXS is reopened and the precharging provides the cell power supply necessary for the datum to be retained.
To read the datum from the cell CEL, the transistor AXS is closed. A current difference is then created between the two bit lines, the sign of which depends on the logic value of the stored datum. This current difference is amplified conventionally in a current amplifier located at the bottom of the column of the memory plane containing the cell, and the datum is thus read.
Such a conventional column of portless, five-transistor SRAM memory cells presents a certain number of drawbacks.
More specifically, during a write operation, the voltage difference between the two bit lines must be sufficiently great to allow the cell to be written to change state, without, however, affecting the stability of the other cells of the same column, since all the cells of the column are powered by these bit lines.
Moreover, during a read operation, the cell read must induce a current difference between the two bit lines that is great enough to be located outside the “offset” of the current amplifier situated at the bottom of the column.
Now, all these constraints are generally incompatible with advanced technologies in which the power supply voltage is relatively low, for example the 45 nanometre technologies in which the power supply voltage is 1.1 volt.